1. Field
Exemplary embodiments of the present invention relate to a nonvolatile memory device, a method for operating the same and a method for fabricating the same, and more particularly, to a nonvolatile memory device which includes a plurality of memory cells vertically stacked from a substrate, a method for operating the same and a method for fabricating the same.
2. Description of the Related Art
A nonvolatile memory device is a memory device which maintains stored data as they are even when power supply is interrupted. Currently, various nonvolatile memory devices, for example, a NAND type flash memory and the like are widely used.
Recently, as improving the degree of integration of a two-dimensional nonvolatile memory device in which memory cells are formed in a single layer on a silicon substrate reaches a limit, a three-dimensional nonvolatile memory device including a plurality of memory cells vertically stacked from a silicon substrate has been variously suggested in the art.
Referring to the paper entitled “Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices,” VLSI Technology, 2009 Symposium, ISBN 978-4-86348-009-4, pp. 136-137, which was disclosed on June 16 to 18, 2009, a flash memory with a PBiCS structure is suggested. In this structure, unlike another conventional three-dimensional nonvolatile memory device including bit lines and source lines respectively disposed over and under stacked memory cells, both bit lines and source lines are located over stacked memory cells. Accordingly, since only one layer of selection gates is needed, advantages are provided in terms of degree of integration, and since the formation of metal source lines is possible, the resistance of the source lines is reduced.
However, because channels are separated from the body of a substrate in the Pipe-shaped BiCS (PBiCS) structure, an erase operation of an F-N tunneling type as in the conventional art, which injects holes into the floating gates of memory cells by applying a high voltage to the body of the substrate, becomes impossible. Instead, data are erased in such a way as to inject holes, which are produced by GIDL (gate induced drain leakage) current flown when a high voltage is applied to selection gates, into channels. Nevertheless, such an erase scheme using GIDL current is difficult to control. An erase operational efficiency deteriorates.
Meanwhile, referring to the paper entitled “Vertical Cell Array using TCAT (Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory,” VLSI Technology, 2009 Symposium, ISBN 978-4-86348-009-4, pp. 192-193, which was disclosed on the same date, a flash memory with a TCAT structure is suggested. In this structure, since channels directly contact the body of a substrate, erase of data as in the conventional art is possible. Furthermore, because word lines are formed through removing sacrificial layers and filling of tungsten in slit structures, advantages are provided in that the resistance of word lines is reduced.
Nonetheless, in the TCAT structure, since source lines are formed in the substrate by performing an ion implantation process through narrow slits, the resistance of source lines may markedly increase.
Consequently, a three-dimensional nonvolatile memory device with a novel structure capable of solving these problems may be demanded in the art.